Many state-of-the-art integrated circuit devices have the capability of operating in one of a variety of different operating modes and include mode selection circuits therein which designate these modes. For example, FIG. 1 illustrates a conventional mode register set circuit for use in memory devices (e.g., DRAM devices). This mode register set circuit 10 includes an address input buffer 101, a mode register 103, a mode register set signal generator 105 and a mode register set signal delay unit 107. The address input buffer 101 receives an external address signal Ai, converts the voltage level of the address signal Ai to a voltage level suitable for the memory device and passes the address signal to the mode register 103. The mode register set signal generator 105 receives external control signals S1, S2 and S3 and generates a mode register set signal MRSET. As will be understood by those skilled in the art, these external control signals may be strobe signals that can be used to control the operating mode of the memory device. The mode register set signal delay unit 107 provides a predetermined amount of delay to the mode register set signal MRSET and generates a delayed version of the mode register set signal MRSET as MRSET.sub.-- D. The mode register 103 receives the address signal Ai and generates a mode selection signal PMODEi in response to the mode register set signal MRSET and the delayed mode register set signal MRSET.sub.-- D. The mode register 103 includes transmission gates 111 and 112, latches 121 and 122, and an inverter 131. Based on this configuration of the mode register, the mode selection signal PMODEi is only generated after the mode register set signal MRSET and the delayed mode register set signal MRSET.sub.-- D are driven to logic 1 levels.
Unfortunately, the conventional mode register set circuit of FIG. 1 generally uses of a plurality of dedicated control signals S1, S2 and S3 which are generated externally. Frequently, however, these plurality of control signals S1, S2 and S3 do not significantly influence operation of the memory device during normal operating modes and the user has the burden of setting the control signals S1, S2 and S3 to generate the mode selection signal PMODEi when using the mode register set circuit. Thus, notwithstanding such integrated circuit devices, there continues to be a need for integrated circuit devices having improved mode selection circuits therein.